There’s an active region between on and off where the current from the collector to emmiter is proportional to the base current. This can be used in other applications like amplifiers. But in digital applications that active region is the transition time between low and high states.

In order to obtain a deterministic outcome the rising edge must be predictable and it must stay at a logic level 1 for long enough to account for propagation delay. These considerations are known as setup and hold. The higher the frequency the clock runs, the tighter these constraints become.

Transistors are only on and off switches when run in saturation. This is relevant to CPUs in the sense that the rising/falling edge and jitter affect the setup and hold times and thus the maximum clock rate. End pedantry.